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? semiconductor components industries, llc, 2002 january, 2002 rev. 3 1 publication order number: ncn6011/d ncn6011 low power level shifter the ncn6011 is a level shifter analog circuit designed to translate the voltages between a sim card and an external microcontroller. the device handles all the signals needed to control the data transaction between the external card and the mpu. features ? 2.7 to 6.0 v input and/or output voltage range ? 500 na quiescent supply current ? all pins are fully esd protected ? supports 10 mhz clock ? provides a logic i/o enable function ? rx/tx communication capability typical applications ? sim/gsm/smartcard interface figure 1. typical interface application 10 9 8 6 7 3 v cc v cc irq p3 p2 p1 mpu or gsm controller 1 2 4 5 reset i/o clock sim_clk sim_rst p0 v dd v supply gnd power management unit v cc i/o_enable sim_io sim_v cc gnd clk rst i/o c4 c8 swb swa v pp 1 5 3 2 7 4 8 18 17 gnd u1 ncn6011 gnd gnd c3 4.7 m f c2 100 nf gnd gnd v dd c1 6.8 f gnd http://onsemi.com tssop14 dtb suffix case 948g 1 10 marking diagrams a = assembly location wl, l = wafer lot y = year ww, w = work week pin connections 2 3 4 5 6 7 14 13 12 10 9 (top view ) reset na i/o vdd clock io_enable na na sim_io sim_rst gnd sim_vcc na 1 11 sim_clk 1 14 1 8 2 3 4 5 10 9 8 6 (top view ) io_enable i/o vdd clock reset sim_io sim_vcc gnd sim_clk 7 sim_rst 1 micro10 tssop14 see detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. ordering information micro10 dm suffix case 846b ncn 6011 alyw 6011 ayw 1 14 1 10
ncn6011 http://onsemi.com 2 2 v dd i/o i/o data data 20 k figure 2. block diagram 1 3 4 5 9 8 7 10 6 sim_v cc 20 k sim_clk sim_rst sim_io ground v dd clock reset i/o gnd gnd (3) (4) (5) (2) (6) (12) (11) (10) (13) (9) sim_v cc i/o_enable gnd notes: 1. numbers in parenthesis adjacent to the pins are related to the tssop14 package. 2. tssop14 package pins 1, 7, 8 and 14 are not connected.
ncn6011 http://onsemi.com 3 abbreviations clock input logic clock reset input logic reset vdd interface power supply input sim_vcc interface ic card power supply output sim_clk interface ic card clock output sim_rst interface ic card reset output sim_io interface ic card i/o signal line class a 5.0 v smart card class b 3.0 v smart card pin descriptions (pin numbers in parenthesis are related to the tssop14 package) (pin numbers in bold are related to the micro10 package) pin name type description (1) na no connection. (tssop14 only) 1 (2) i/o input this pin is connected to an external microcontroller. a bidirectional level translator adapts the serial i/o signal between the smart card and the external controller. a builtin constant 20 k w typical resistor provides a high impedance state when not activated. 2 (3) v dd power this pin is connected to the system controller power supply and the input voltage can range from 2.7 to 6.0 v. 3 (4) clock input the clock signal, coming from the external controller, must have a duty cycle within the min/max limits defined by the specification (typically 50%). the builtin level shifter translates the input signal to the external sim card voltage supply. 4 (5) reset input the reset signal present at this pin is provided by the mpu. the internal level shifter translates the level according to the voltages applied to pin 3 and pin 12. 5 (6) io_enable input this logic input pin forces sim_io pin to low when io_enable = low, leaving this signal high when io_enable = high. the signal is not latched and the sim_io pin is released to a logic high when io_enable = high. when this condition is met, the sim_io logic status depends upon the signal presence pin i/o. when the mpu uses two different channels to exchange data with the sim card, the io_enable pin can be used to as a write line to the external card, the i/o pin being used to read data from the sim card. (7) na no connection. (tssop14 only) (8) na no connection. (tssop14 only) 6 (9) gnd ground this pin is the ground reference for the integrated circuit and associated signals. high frequency layout techniques are requested to connect the gnd pin to the external functions. 7 (10) sim_rst output this pin is connected to the rst pin of the card connector. a voltage level translator adapts the external reset signal (coming from the mpu) to the smart card. 8 (11) sim_clk output this pin is connected to the clk pin of the card connector. the clock signal comes from the external clock generator. the internal voltage level shifter adapts the clock signal flowing through this link. care must be observed to prevent ac coupling with adjacent lines and signals pcb tracks. 9 (12) sim_vcc power this pin is connected to the smart card vcc power supply pin. the voltage, provided by an external power supply, can range from 2.7 v to 6.0 v. the ncn6011 does not regulate or protect the voltage supply applied to the external card. 10 (13) sim_i/o output this pin handles the connection to the serial i/o of the card connector. a bidirectional voltage level translator adapts the serial i/o signal between the card and the microcontroller. a 20 k w typical pull up resistor provides a high impedance state for the sim card i/o link. (14) na no connection. (tssop14 only)
ncn6011 http://onsemi.com 4 maximum ratings rating symbol value unit power supply v dd 7.0 v v external card and level shifter power supply sim_vcc 7.0 v v digital input voltage digital input current reset, io_enable 0.3 v v dd 1.0 v ma digital input voltage digital input current clock 0.3 v v dd 1.0 v ma digital input voltage digital input current i/o 0.3 v v dd 1.0 v ma digital output voltage digital output current sim_rst 0.3 v sim_vcc 25 v ma digital output/input voltage digital output/input current sim_i/o 0.3 v sim_vcc 25 v ma digital output voltage digital output current sim_clk 0.3 v sim_vcc 50 v ma human body model: r = 1500 w , c = 100 pf sim card side, pins 7, 8, 9, 10 (10, 11, 12, 13) all other pins esd 4.0 2.0 kv kv micro10 package power dissipation @ t a = +85 c thermal resistance junction to air p d r thhja 200 200 mw c/w tssop14 package power dissipation @ t a = +85 c thermal resistance junction to air p d r thhja 320 125 mw c/w operating ambient temperature range t a 25 to +85 c operating junction temperature range t j 25 to +125 c maximum junction temperature t jmax +150 c storage temperature range t stg 65 to +150 c maximum electrical ratings define the values beyond which permanent damage(s) may occur internally to the chip regardless of th e operating temperature. pin numbers in parenthesis are related to the tssop14 package.
ncn6011 http://onsemi.com 5 power supply section (25 c to +85 c ambient temperature, unless otherwise noted) (pin numbers in parenthesis are related to the tssop14 package) (pin numbers in bold are related to the micro10 package) rating symbol pin min typ max unit power supply v dd 2 (3) 2.7 6.0 v standby supply current, clock = l, i/o = h, sim_vcc = 3.0 v, no sim card inserted i vdd 2 (3) 0.5 2.0 m a input external power supply sim_vcc 9 (12) 2.7 6.0 v standby current, sim_vcc = 3.0 v, i/o = h, no sim card inserted, clock = l i vcc 9 (12) 0.2 0.5 m a power supply normal operating current @ vdd = +5.0 v, sim_vcc = +5.0 v, clock = 5.0 mhz, reset = h, io_enable = h, i/o data = 100 khz i dd 2 (3) 230 m a power supply normal operating current @ vdd = +5.0 v, sim_vcc = +5.0 v, clock = 5.0 mhz, reset = h, io_enable = h, i/o data = h i dd 2 (3) 80 m a card level shifter operating current @ vdd = +5.0 v, sim_vcc = +5.0 v, clock = 5.0 mhz, reset = h, io_enable = h, i/o data = 100 khz i cc 9 (12) 1.50 ma card level shifter operating current @ vdd = +5.0 v, sim_vcc = +5.0 v, clock = 5.0 mhz, reset = h, io_enable = h, i/o data = h i cc 9 (12) 1.30 ma digital input section: clock, reset, i/o, io_enable (25 c to +85 c ambient temperature, unless otherwise noted) (note 1) rating symbol pin min typ max unit clock, reset, io_enable high level input voltage low level input voltage input rise time input fall time input capacitance v ih v il tr tf cin 1, 3, 4, 5 (2, 4, 5, 6) 0.7 * v dd v cc 0.3 * v dd 50 50 10 v v ns ns pf input @ duty cycle = 50% 1% (note 2) clock rise time clock fall time input clock capacitance clock 3 (4) 5.0 50 50 10 mhz ns ns pf input/output data transfer frequency i/o rise time i/o fall time input i/o capacitance i/o 1 (2) 160 0.8 0.8 10 khz m s m s pf 1. digital inputs undershoot 0.30 v, digital inputs overshoot 0.30 v. 2. the sim_clk clock can operate up to 10 mhz, but, in this case, the rise and fall time are not guaranteed to be fully within t he gsm specification over the temperature range.
ncn6011 http://onsemi.com 6 sim interface section (note 3) rating symbol pin min typ max unit sim_vcc = +5.0 v output reset v oh @ irst = +200 m a output reset v ol @ irst = 200 m a output reset rise time @ cout = 30 pf output reset fall time @ cout = 30 pf sim_vcc = +3.0 v output reset v oh @ irst = +200 m a output reset v ol @ irst = 200 m a output reset rise time @ cout = 30 pf output reset fall time @ cout = 30 pf sim_rst 7 (10) sim_vcc 0.7 v 0 0.8 * sim_vcc 0 sim_vcc 0.6 100 100 sim_vcc 0.2 * sim_vcc 100 100 v v ns ns v v ns ns sim_vcc = +5.0 v output duty cycle @ fin = 5.0 mhz dc = 50% 1% output sim_clk rise time @ cout = 30 pf output sim_clk fall time @ cout = 30 pf output v oh @ iclk = +20 m a output v ol @ iclk = 200 m a sim_vcc = +3.0 v output duty cycle @ fin = 5.0 mhz dc = 50% 1% output sim_clk rise time @ cout = 30 pf output sim_clk fall time @ cout = 30 pf output v oh @ iclk = +20 m a output v ol @ iclk = 20 m a sim_clk 8 (11) 40 0.7 * sim_vcc 0 40 0.7 * sim_vcc 0 60 18 18 sim_vcc +0.5 60 18 18 sim_vcc 0.2 * sim_vcc % ns ns v v % ns ns v v sim_vcc = +5.0 v @ io_enable = h sim_i/o data transfer frequency sim_i/o rise time @ cout = 30 pf sim_i/o fall time @ cout = 30 pf output v oh @ isim_io = +20 m a, v ih = v dd output v ol @ isim_io = 1.0 ma, i/o v il = 0 v sim_vcc = +3.0 v @ io_enable = h sim_i/o data transfer frequency sim_i/o rise time @ cout = 30 pf sim_i/o fall time @ cout = 30 pf output v oh @ isim_io = +20 m a, v ih = v dd output v ol @ isim_io = 1.0 ma, i/o v il = 0 v sim_vcc = +5.0 v @ io_enable = l sim_i/o fall time @ cout = 30 pf output v ol @ isim_io = 1.0 ma, i/o v il = 0 v sim_vcc = +3.0 v @ io_enable = l sim_i/o fall time @ cout = 30 pf output v ol @ isim_io = 1.0 ma, i/o v il = 0 v sim_vcc = +5.0 v @ i/o = h, io_enable returns to high sim_i/o rise time @ cout = 30 pf sim_vcc = +3.0 v @ i/o = h, io_enable returns to high sim_i/o rise time @ cout = 30 pf sim_i/o 10 (13) 0.7 * sim_vcc 0 0.7 * sim_vcc 0 0 0 150 150 2.0 1.5 160 0.8 0.8 sim_vcc 0.4 160 0.8 0.8 sim_vcc 0.4 800 0.4 800 0.4 khz m s m s v v khz m s m s v v ns v ns v m s m s i/o pull up resistor i/o_ rpld 1 (2) 13 20 k w card i/o pull up resistor sim_i/o_ rpld 10 (13) 13 20 k w 3. sim logic input undershoot 0.30 v, sim logic input overshoot 0.30 v.
ncn6011 http://onsemi.com 7 200 100 250 50 150 0 300 1200 2 80 5 4 3 i dd ( m a) 0 v dd (v) figure 3. sim supply current as a function of the v dd voltage, i/o = high figure 4. sim supply current as a function of the v dd voltage, i/o = 100 khz data transfer i dd ( m a) 2 1600 1400 1200 1000 4 3 800 600 400 200 0 56 figure 5. power supply current as function of the v cc input voltage, i/o = high v dd (v) figure 6. power supply current as function of the v cc input voltage, i/o = 100 khz data transfer v dd (v) i cc ( m a) i cc ( m a) 120 800 1400 600 1000 0 1600 1800 5 mhz v dd (v) 20 40 60 100 6 3 mhz 1 mhz 25 4 36 5 mhz 3 mhz 1 mhz 400 200 24 356 5 mhz 3 mhz 1 mhz 5 mhz 3 mhz 1 mhz
ncn6011 http://onsemi.com 8 level shifters the builtin level shifters accommodate the differential voltage between the external mpu and the sim card. neither the logic nor the functions of the sim signals are affected by the interface. the ncn6011 does not regulate the sim_vcc, nor does it detect the overload current. bidirectional level shifter the ncn6011 carries out the voltage difference between the mpu and the smart card i/o signals. when the start sequence is completed, and if no failures have been detected, the device becomes essentially transparent for the data transferred on the i/o line. to fulfill the iso78163 specification, both sides of the i/o line have builtin pulsed circuitry to accelerate the signal rise transient. the i/o line is connected on both sides of the interface by a nmos switch which provide the level shifter and, thanks to its relative high internal impedance, protects the sm art card in the event of data collision. such a situation could occur if either the mpu of the smart card forces a signal in the opposite logic level direction. q1 q2 gnd v dd i/o 200 ns 20 k 20 k sim_io q5 v cc logic i/o control enable figure 7. basic internal i/o level shifter 200 ns gnd figure 8. typical i/o and sim_io waveform, v dd = v cc = 5.0 v, enable = low figure 9. typical sim_io activated by enable pin, i/o = high (open drain) i/o sim_io enable sim_io
ncn6011 http://onsemi.com 9 input schmitt triggers all the logic input pins have builtin schmitt trigger circuits to prevent the ncn6011 against uncontrolled operation. the typical dynamic characteristics of the related pins are depicted in figure 10. the output signal is guaranteed to go high when the input voltage is above 0.70*vbat, and will go low when the input voltage is below 0.30*vbat. output v bat on off v bat 0.70 *v bat figure 10. typical schmitt trigger characteristic input 0.30 *v bat esd protection the ncn6011 includes silicon devices to protect the pins against the esd spikes voltages. to cope with the different esd voltages developed across these pins, the builtin structures have been designed to handle either 2.0 kv, when related to the microcontroller side, or 4.0 kv when connected with the external contacts. practically, the sim_rst, simd_clk and sim_io pins can sustain 4.0 kv. printed circuit board layout since the ncn6011 carries high speed currents together with high frequency clock, the printed circuit board must be carefully designed to avoid the risk of uncontrolled operation of the interface. care must be observed to avoid common copper track sharing small signal and high power with a relative high impedance. on top of that, the clock signal (both input and output) shall be properly shielding to minimize the high frequency cross talk between this line and the rest of the circuit. in particular, the sim_rst signal shall be protected from interference generated by the sim_clk line. such protection can be achieved by surrounding the sim_clk track by a copper track connected to ground. generally speaking, the ground plane shall be as large as possible for a given printed circuit board area. 14 13 12 10 9 8 11 3 figure 11. typical ncn6011/tssop14 application v cc v cc irq p3 p2 p1 mpu or gsm controller 1 2 4 5 6 7 reset i/o clock na sim_clk sim_rst p0 na v dd v supply gnd power management unit v cc i/o_enable na sim_io sim_v cc na gnd clk rst i/o c4 c8 swb swa v pp 1 5 3 2 7 4 8 18 17 v dd c1 6.8 m f gnd gnd u1 ncn6011 gnd gnd c3 4.7 m f c2 100 nf gnd gnd
ncn6011 http://onsemi.com 10 ordering information device package shipping ncn6011dtb tssop14 96 units/rail ncn6011dtbr2 tssop14 2500 tape & reel ncn6011dmr2 micro10 4000 tape & reel
ncn6011 http://onsemi.com 11 package dimensions tssop14 dtb suffix case 948g01 issue o dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c --- 1.20 --- 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.50 0.60 0.020 0.024 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. s u 0.15 (0.006) t 2x l/2 s u m 0.10 (0.004) v s t l u seating plane 0.10 (0.004) t ?? ?? ?? section nn detail e j j1 k k1 detail e f m w 0.25 (0.010) 8 14 7 1 pin 1 ident. h g a d c b s u 0.15 (0.006) t v 14x ref k n n micro10 dm suffix case 846b02 issue b s b m 0.08 (0.003) a s t dim min max min max inches millimeters a 2.90 3.10 0.114 0.122 b 2.90 3.10 0.114 0.122 c 0.95 1.10 0.037 0.043 d 0.20 0.35 0.008 0.014 g 0.50 bsc 0.020 bsc h 0.05 0.15 0.002 0.006 j 0.10 0.21 0.004 0.008 k 4.75 5.05 0.187 0.199 l 0.40 0.70 0.016 0.028 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a" does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b" does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. 846b-01 obsolete. new standard 846b-02 b a d k g pin 1 id 8 pl 0.038 (0.0015) t seating plane c h j l
ncn6011 http://onsemi.com 12 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. ncn6011/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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